196,437 research outputs found
WGMS Broadcast: SDS Attack on Mayor Joseph L. Alioto, March 1969
No full textRepository: Booth Family Center for Special Collections. For more information about this collection please email: [email protected] segment on WGTB FM, "The Voice of Georgetown University", opens with the voice of Frederick J. "Fred" Slowick (F 1972). A special report by Peter Bary Chowka (C 1971) describes disruptions by students, mostly from other Washington schools, to an appearance by San Francisco Mayor Joseph Alioto in Gaston Hall earlier that evening. The report includes a recording of protestors chanting outside Gaston Hall as Mayor Alioto arrives and as they later attempt to gain access to the Hall. The recording also includes an interview with Richard McSorley, S.J., who speaks at the 7 minute 42 second mark about reasons for the protests. James "Jim" M. Illig (C 1970), the Public Affairs Director of WGTB, is also heard introducing a recording of a press conference given by Mayor Alioto in "a secluded part of the university" after he had been forced from Gaston Hall and a subsequent message from the Mayor to Georgetown University students
Analysis of Layout Density in FinFET Standard Cells and Impact of Fin Technology
No full textIn this paper, the layout density of three-terminal FinFET logic circuits is extensively analyzed. As opposite to previous works, which are focused either on single devices or simplistic circuits, this analysis explicitly includes the geometric constraints that are imposed by the standard cell approach. The impact of the fin technology is analyzed by comparing the lithography- and spacer-defined approaches, as well as evaluating the dependence of layout density on the fin height.
Results show that FinFET standard cells have a layout density that is better than bulk cells even for moderately tall fins. The fin height is also shown to be a powerful knob to improve the layout density in FinFET cells. Analysis also shows that the usually claimed 2X density improvement of the spacer-defined technology compared to the lithography-defined is dramatically reduced in real standard cells, and can be negligible for tall fins. All results are justified through considerations at the physical level of abstraction. Various versions of a 32-nm 44-gate library are laid out to carry out the analysis
Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools
No full textIn this paper, models of the input admittance of RC interconnects are discussed in depth to understand and evaluate their loading effects on the driving CMOS gates. From the detailed analysis of the input admittance pole-zero location, arguments are derived to prove that their input admittance can be accurately approximated to that of a low-order equivalent RC circuit, in contrast to the case of timing analysis of RC wires. More specifically, 1st- or 2nd-order equivalent circuits are derived analytically via the moment matching approach, as opposite to previous analyses that rely on purely numerical approaches. Moreover, simple analytical rules to extend results to arbitrarily complex networks are derived, as opposite to the usual approach that requires the numerical estimation of moments. Being fully analytical, the proposed approach permits to develop models that are extremely simple (i.e., computationally efficient), as well as to gain an insight into the properties of the input admittance of RC interconnects.
The proposed equivalent circuits are evaluated and validated in situations that occur in real CAD design flows, where RC wire loading effects are estimated by CAD tools to perform the timing/power analysis of the buffer driving the wire. The analysis is validated through extensive simulations on a 65-nm CMOS technology. Well-defined criteria are also derived to select the appropriate model of the RC wire input admittance for accurate timing/power estimations in VLSI CAD tools
Analysis and design of MCML gates with hysteresis
No full textIn this paper, hysteresis is exploited to improve the performance of positive feedback source coupled logic circuits, which are a modification of the traditional MOS current-mode logic (MCML) (Alioto, 2004). To understand the effect of hysteresis on the DC characteristics, a model of the noise margin is analytically derived. This model shows that hysteresis improves the noise margin, whose increase is traded-off to reduce the logic swing, which in turn can have a beneficial impact on the speed performance. Practical cases where hysteresis is advantageous are identified, and a comparison with PFSCL gates without hysteresis is carried out. Analysis shows that in such cases hysteresis significantly improves the speed performance and the power efficiency of PFSCL gates, which is a critical aspect in this kind of logic. Simulation results are presented based on a 0.18-mum CMOS proces
CAD Models of the Input Admittance of RC Wires: Comparison and Selection Strategies
No full textIn this paper, CAD models of the input admittance of RC interconnects are discussed. To this aim, properties of RC circuits are exploited to show that the input admittance of RC wires is approximated very well by that of a low order RC circuit, as opposite to the timing modeling of RC wires. In particular, 1(st)- or 2(nd)-order equivalent circuits are shown to be sufficient for fast and accurate estimations of the loading effects associated with RC wires. The accuracy of these models is evaluated and compared in various practical situations that occur in automated design flows, i.e. in the evaluation of the main timing/power parameters of buffers loaded by an RC wire (e.g., delay, peak supply current, ...). This allows for understanding the suitability of each model for fast and accurate estimations of the loading effects of RC wires on buffers. Finally, a simple criterion to select the most suitable model of these loading effects is proposed for each parameter of interest in current CAD tools for VLSI design
Closed-Form Analysis of DC Noise Immunity in Subthreshold CMOS Logic Circuits
No full textIn this paper, subthreshold static CMOS logic is analyzed in terms of DC noise immunity in a closed form for the first time. Simplified circuit models of MOS transistors in subthreshold are developed to gain a deeper understanding of the degradation in the DC characteristics under ultra-low voltages, as well as its dependence on design and process parameters. The noise margin is explicitly evaluated and modeled with a simple expression. The impact of PMOS/NMOS imbalance is also explicitly analyzed. Results are validated with simulations in a 65-nm CMOS technology
A Simple and Accurate Model of Input capacitance for Power Estimation in CMOS logic
No full textIn this paper, an analytical model of the input capacitance of nanometer CMOS gates is proposed. The model accounts for the non-linear behavior of the gate capacitance in sub-100 nm technologies, and allows to gain an insight into the dependence on the supply voltage. Its application to power modeling is explicitly dealt with.
The model is fully analytical hence no look-up tables are needed to implement it. Moreover, it is simple and does not require simulations or fitting parameters, thus it is well suited for efficient gate-level modeling in automated design. The model is shown to agree well with circuit simulation results, as an error as low as a few percentage points is found for a 90-nm CMOS technology
Impact of NMOS/PMOS Imbalance in Ultra-Low Voltage CMOS Standard Cells
No full textIn this paper, the impact of the NMOS/PMOS imbalance on Ultra-Low Voltage (ULV) circuits and their design is discussed within a unitary framework for the first time. Variations are shown to dramatically affect imbalance due to the long-tailed probability density and high variability.
The impact of the imbalance on the minimum supply voltage VDD,min ensuring correct gate switching is studied analytically. The results theoretically justify the experimental results in [1], which agree very well with the predictions. The impact of the imbalance on the leakage energy in VLSI systems is also analyzed through a simple but representative example. An analytical model is presented to predict such leakage energy increase due to imbalance. Extensive results in 65-nm CMOS are shown to agree with the design considerations and quantitative models presented
NAND/NOR Adiabatic Gates: Power Consumption Evaluation and Comparison versus the Fan-In
No full textIn the paper the buffer and the NAND/NOR adiabatic gate are compared with that designed with the traditional CMOS approach. The comparison is made both assuming an assigned power supply and setting its value to minimize the power consumption. General relationship independent from process parameter, which are also simple to be useful in a pencil-and-paper evaluation, are carried out.
Analytical results are validate with Spice Simulations by using 0.8-m CMOS technology. The analysis show that with the considered technology and a fan-out of three, the adiabatic buffer is advantageous for frequency lower than 167 MHz and 21 MHz for the non optimized and the optimized design, respectively. These frequencies lower to 23 MHz and 1.3 MHz for the NAND/NOR gate. Moreover all the frequency reduce linearly increasing the fan out of the gate
Delay Uncertainty Due to Supply Variations in Static and Dynamic Full Adders
No full textIn this paper, the delay uncertainty due to supply variations is investigated for two important Full Adder topologies. In particular, it is developed an analytical model of the delay sensitivity to supply variations for the static Mirror adder and the dynamic Dual-Rail Domino adder. The model is general and very simple, and allows for identifying the main parameters which define the delay uncertainty due to supply variations, as well as deriving design considerations. In particular, the importance of the input rise/fall time variations is clarified, and the effect of the supply voltage reduction and technology scaling is discussed. Results are validated through SPICE simulations with a 0.18-mu m and a 0.35-mu m technology
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