1,720,993 research outputs found
Physics of Phase Transition Switches
No full textThe semiconductor industry is undergoing an epochal shift, driven by the move to pseudo-three- (2.5D) and three-dimensional (3D) packaging of integrated circuits based on non-scalable classical Boltzmann transistors. In this regard, the scaling potential of post-Boltzmann phase-transition logic switches, memory elements, super-Nernstian sensors, and zero-energy displays remains underappreciated. Broadly defined, phase-transition switches operate between two stable states separated by an energy or power barrier, offering promising solutions for the future of electronics. This tutorial paper provides a foundational and intuitive understanding of the emerging field of phase-transition electronics. It also highlights open issues and research opportunities, serving as a roadmap for advancing this critical technology
Reliability of HfO2-Based Ferroelectric FETs: A Critical Review of Current and Future Challenges
Full text linkFerroelectric transistors (FeFETs) based on doped
hafnium oxide (HfO2) have received much attention due to
their technological potential in terms of scalability, highspeed,
and low-power operation. Unfortunately, however,
HfO2-FeFETs also suffer from persistent reliability challenges,
specifically affecting retention, endurance, and variability. A
deep understanding of the reliability physics of HfO2-FeFETs is
an essential prerequisite for the successful commercialization
of this promising technology. In this article, we review the
literature about the relevant reliability aspects of HfO2-FeFETs.
We initially focus on the reliability physics of ferroelectric
capacitors, as a prelude to a comprehensive analysis of FeFET
reliability. Then, we interpret key reliability metrics of the FeFET
at the device level (i.e., retention, endurance, and variability)
based on the physical mechanisms previously identified.
Finally, we discuss the implications of device-level reliability
metrics at both the circuit and system levels. Our integrative
approach connects apparently unrelated reliability issues and
suggests mitigation strategies at the device, circuit, or system
level. We conclude this article by proposing a set of research
opportunities to guide future development in this field
Self-Heating and Reliability-Aware “Intrinsic” Safe Operating Area of Wide Bandgap Semiconductors – An Analytical Approach
Full text linkThe emergence of several technology options and the ever-broadening range of applications (e.g., automotive, smart grids, solar/wind farms) for power electronic devices suggest both a need and an opportunity to develop unifying principles to guide the development of wide bandgap (WBG) semiconductors. Unfortunately, power electronic devices are typically evaluated with a variety of elementary figure of merits (FOMs), which offer inconsistent/contradictory projections regarding the relative merits of emerging technologies. Indeed, one relies on the empirical (extrinsic) safe-operating area (SOA) of a packaged device to ultimately assess the performance potential of a technology option. Unfortunately, extrinsic SOA can only be calculated a posteriori, i.e., after precise measurement of the fabricated device parameters, making it suitable only for relatively mature technologies. Based on the insights of material-device-circuit-system performance analysis of a variety of idealized WBG power electronic devices (e.g., GaN HEMT, β-Ga2O3 MOSFET), in this paper, we analytically derive a comprehensive, substrate-, self-heating-, and reliability-aware “intrinsic/limiting” safe operating area (SOA) that establishes a priori, i.e., before device fabrication, the optimum and self-consistent trade-off among breakdown voltage, power consumption, operating frequency, heat dissipation, and reliability. We establish the relevance of the intrinsic-SOA by comparing its prediction with a broad range of experimental data available in the literature. In between the traditional FOMs and extrinsic SOA, the intrinsic SOA allows fundamental/intuitive re-evaluation of intrinsic technology potential for power electronic devices and identifies specific performance bottlenecks and how to circumvent them
Multi-probe experimental and \u27bottom-up\u27 computational analysis of correlated defect generation in modern nanoscale transistors
No full textAs transistors are getting smaller, it has become increasingly difficult to achieve requisite device performance for new generations of ICs. Two approaches are being considered: Replacing Si-SiO2 transistors with higher performance III-V transistors, or operating the classical transistors close to their reliability limits. In the first part of the thesis, we consider the problem of interface defects with various combinations of gate oxides and substrate materials. We use a combination of characterization techniques to profile the interface and bulk defects in both position and energy, and also to understand how the defect charge level changes with its occupation probability. This multi-probe analysis is necessary to differentiate between the acceptor- and donor-like defects and to obtain an accurate estimate of the defect densities. We show that the nature of the defect (acceptor-like vs. donor-like) at In 0.65Ga0.35As/Al2O3 interface plays a significant role in determining whether surface inversion is possible for these novel transistor structures. In the second part, we consider the problem of reliability close to the physical limit where classical perspectives must be supplemented by ‘bottom-up’ considerations. The reliability studies are traditionally carried out as stand-alone analysis at specific operating bias conditions like NBTI, HCI, and TDDB. The defect generation at various bias conditions however depends on parameters like carrier densities, process conditions, material properties etc., and therefore should be a part of the reliability analysis. As a specific example to the general “bottom-up” approach we propose, we study the non-classical OFF-state degradation in Drain Extended MOS (DeMOS) transistors. These transistors show correlated parameter degradation and dielectric breakdown when biased in OFF-state conditions (VG=0V, :VD :\u3e5V) and as such defy classical reliability classification. We show that the OFF-state degradation in DeMOS transistors is due to interfacial ≡Si„ŸO bonds broken by hot carriers generated from band-to-band tunneling followed by impact ionization. The resultant degradation exhibits a unique scaling law, which enables accurate lifetime extrapolation based on short term measurements. The saturating nature of the degradation curve is explained based on bond-dispersion (B-D) model, which assigns a finite spread to the ≡Si—O bond energy within the amorphous SiO2. OFF-state TDDB is shown to be due to ≡Si—O bonds broken in the bulk of the oxide by exactly identical mechanism, and is therefore shown to correlate with interface damage. The breakdown statistics of the OFF-state TDDB is consistently explained based on asymmetric percolation model. The generalized approach thus explains the correlated degradation in DeMOS transistors and significantly reduces the characterization time and cost. The above framework to analyze non-classical OFF-state degradation is however general and is not limited to a specific operating condition or device structure. We therefore analyzed ON-state hot carrier degradation in DeMOS transistors based on the bottom-up approach and verified that the basic degradation mechanism and features of OFF-state degradation remain invariant in spite of the orders of magnitude increase in drain current. We also studied ON-state degradation in logic transistors from various technology nodes, and remarkably the universality of hot carrier degradation is shown to be valid even for the ultra-scaled transistors operating at much lower operating biases. Classical hot carrier models cannot be used to analyze hot carrier degradation in these ultra-scaled transistors as the substrate current is contaminated by excessive gate leakage. Instead, we demonstrate how the universality of hot carrier degradation can be used to perform fast and accurate hot carrier lifetime extrapolation based on short-term measurements. Our multi-probe experimental and “bottom-up” computational approach thus provides new insights into the defect generation at oxide/substrate interface and provides a model independent methodology for hot carrier lifetime extrapolation
Modeling and Fundamental Design Considerations for Portable, Wearable and Implantable Electronic Biosensors
Full text linkChronic diseases such as cancer, diabetes, acquired immune deficiency syndrome (AIDS), etc. are leading causes of mortality all over the world. Portable, wearable and implantable biosensors can go a long way in preventing these premature deaths by frequent or continuous self-monitoring of vital health parameters
Electro-Thermal and Radiation Reliability of Power Transistors: Silicon to Wide Bandgap Semiconductors
No full textWe are in the midst of a technological revolution (popularly known as Industrie 4.0 or 4th Industrial Revolution) where our cars are being equipped with hundreds of sensors that make them safer, homes are becoming smarter, industry yields are at an all-time high, and internet-of-things is a reality. This was largely possible due to the developments in communication, electronics, motor controls, robotics, cyber security, software, efficient power distribution, etc. One of the major propellants of the 4th Industrial revolution is the ever-expanding applications of power electronics devices. All electrical energy will be provided, handled, and consumed through power electronics devices in the near future. Therefore, the reliability of power electronics devices will be instrumental in driving future technological advances.A myriad of devices is categorized as power electronics devices, and in the heart of those devices are the transistors. Although Silicon-based transistors still dominate the power electronics market, a paradigm shift towards wide bandgap semiconductors, such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (β-Ga2O3), etc., is underway. However, realizing the full potential of these devices demands unconventional design, layout, and reliability.In this thesis, we try to establish a generalized model of reliability for power and logic transistors. We start by defining a comprehensive, substrate-, self-heating-, and reliability-aware safe operating area (SOA) that analytically establishes the optimum and self-consistent trade-off among breakdown voltage, power consumption, operating frequency, heat dissipation, and reliability before actual device fabrication. Then we take a deeper look into the reliability of individual transistors (a β-Ga2O3 transistor and a Silicon-based LDMOS), to test the predictions by the safe operating area, using both experiments and simulations. In the β-Ga2O3 transistor, we studied its implementation in a DC-DC voltage converter and concluded that the self-heating is a performance bottleneck and suggested approaches to alleviate it. For the LDMOS transistor, we investigated the hot carrier degradation (HCD) using experiments and simulations. We established that the HCD degradation kinetics is universal, and physics is the same as a classical transistor, despite a complicated geometry.Finally, we studied the correlation between HCD and radiation in LDMOS used in space shuttles, airplanes, etc., to determine its lifetime.We have holistically analyzed the reliability of power transistors by extending the theories of logic transistors in this thesis. Therefore, this thesis takes us a step closer to a generalized reliability model for power transistors by developing a comprehensive and predictive model for the safe operating area, encompassing all sources of stresses (e.g., electrical, thermal, and radiation) it experiences during operation
System-Level Performance and Reliability of Solar Photovoltaic Farms: Looking Ahead and Back
No full textIn a world of ever-increasing demand for energy while preventing adverse effects of climate change, renewable energy has been sought after as a sustainable solution. To this end, the last couple of decades have seen an advancement in research and development of solar photovoltaic (PV) technology by leaps and bounds. This has led to a steady improvement in the cost-effectiveness of solar PV as compared to the traditional sources of energy, e.g., fossil fuels as well as contemporary renewable energy sources such as wind and hydropower. To further decrease the levelized cost of energy (LCOE) of solar PV, new materials and technologies are being investigated and subsequently deployed as residential, commercial, and utility-scale systems. One such innovation is called bifacial PV, which allows collection of light from the front as well as rear surfaces of a flat PV panel.In this thesis, we present a detailed investigation of bifacial solar PV farms analyzed across the globe. We define the problem, explore the challenges, and collaborate with researchers from academia and the PV industry to find a novel solution.First, we begin by developing a multi-module computational framework to numerically model a utility-scale bifacial solar PV farm. This requires integrating optical, electrical, thermal, and economic models in order to estimate the energy yield and LCOE of a bifacial PV system. The first hurdle is to re-formulate the LCOE so that the economist and the technologist can collaborate seamlessly. Thus, we re-parameterize the LCOE expression and validate our economic model with economists at the National Renewable Energy Lab (NREL).Second, we extend the existing optical and electrical models created for stand-alonebifacial PV panels to models that can simulate a large-scale bifacial solar PV farm. This brings the challenge of mathematically modeling solar farms and light collection on the rows of PV panels elevated from the ground by taking into account the mutual shading between the rows, reflections from the ground, and elevation-dependent light absorption on the rear surface of the PV panels from several neighboring rows. Next, we integrate temperaturedependent efficiency models to take into account the effects of location-dependent ambient temperature, wind speed, and technology-varying temperature coefficients of the solar PV system in consideration.Third, we complete the comprehensive modeling of bifacial solar PV farms by including two types of single-axis tracking algorithms viz. sun-tracking and power tracking. Using these algorithms, we explore the best tracking orientation of solar farms i.e., East-West tracking vs. North-South tracking for locations around the world. We further find the best land type suitable for installation of these E/W or N/S tracking bifacial solar PV farms.Fourth, we reduce the computation time of numerical modeling by utilizing the advantages of machine learning algorithms. We train neural networks using data from the alreadybuilt models to emulate the numerical modeling of a solar farm. Amazingly, we find the computation time reduces by orders of magnitude while accurately estimating the energy yield and LCOE of PV farms.Fifth, we derive, compare, and experimentally validate the thermodynamic efficiency limits of photovoltaic-to-electrochemical energy conversion for the purpose of storing solar energy for future needs.Finally, we present some new ideas and guidelines for future extensions of this thesis as well as new challenges and problems that need further exploration
Reliability Characterizations of Power Transistors: from Silicon to Oxide Semiconductors
No full textSemiconductor power electronics find widespread use in miscellaneous applications, including power management in smart grids, electrical motors in self-driving cars, satellite power systems, and so on. In these high voltage systems, it is inevitable that the reliability issues at the transistor level, e.g., hot carrier degradation (HCD), bias temperature instability (BTI), and self-heating effect (SHE), would be prominent and must be carefully investigated. The geometrical and doping complexities of power transistors make their reliability issues very distinct from classical low-voltage logic transistors. Other than the classical material such as Si, commercialized wide bandgap (WBG) materials such as GaN and SiC, and emerging oxide semiconductors such as β-Ga2O3 and In2O3 have attracted researchers’ attention. For example, β-Ga2O3’s ultra-wide bandgap (4.6 to 4.9 eV) makes it a promising candidate to compete with GaN and SiC. Amorphous In2O3, grown by atomic layer deposition (ALD), is demonstrated to possess high electron mobility (\u3e100 cm2V−1 s −1). The reliability issues of the two emerging materials are worth exploring. As a result, this thesis can be divided into two major parts: silicon and oxide semiconductor. Our main contributions are new characterization techniques and reliability models, which are essential for integrated power systems.In the first part of the thesis, the localized HCD in Si-based lateral diffused MOSFETs (LDMOSs) with different geometries and structures are explored by two new characterization methods. The first one is called ”three-point I-V spectroscopy” and the other is called ”Super Single Pulse Charge Pumping (S2PCP)”. The former technique extracts the mobility degradation percentage (∆µ) in the channel and drift regions individually. The latter extracts the localized interface trap generation (∆Nit). S2PCP is developed for the source-body-tied (SBT) LDMOS, in which the classical charge pumping techniques cannot function properly. The results from the two techniques compare well with each other, providing cross-validation of the techniques. For different types of LDMOS transistors under study, the channel region degradation is enhanced under higher VG bias. This channel degradation was then observed to be HCD-assisted anode hole injection (AHI) because of the stronger recovery, positive temperature activation, and negligible temperature dependence in gate leakage.In the second part of the thesis, two emerging oxide semiconductors, β-Ga2O3 and In2O3 are studied. For β-Ga2O3, SHE is identified as a critical issue due to its low thermal conductivity. Therefore, the self-heating was included in circuit simulations, and indeed reveals a degradation in the efficiency of DC-DC boost conversion. The thermal resistance (θth) of the bilayered structure is modeled, and its maximum current (Imax) and power (Pmax) metrics are derived and estimated through analytical calculations. The choice of high-thermalconductivity substrate, wafer thinning, etc, can help in mitigating SHE. However, extra effort is still vital to further improve β-Ga2O3 performance to outperform GaN and SiC. On the other hand, 1.2-nm-thick amorphous In2O3thin-film transistors (TFTs) demonstrate promising electrical performances. Grown in a relatively low temperature (∼225 °C), it is recognized as a back-end-of-line (BEOL) compatible transistor. The reliability studies such as positive bias temperature stress (PBTS) and HCD are explored and modeled. Unlike traditional logic transistors, HCD is strongly correlated to PBTS, which is caused by the much stronger vertical field compared to the lateral field in the ultra-thin devices. Overall, the high-performance BEOL-TFTs are remarkably reliable, with a relatively small threshold voltage shift under PBTS/HCD stress conditions at room temperature
Droplet-based Impedance Sensing for Biomedical Applications and Probing Bacterial Response to Environmental Stressors
No full textAccording to the World Health Organization, every year around 60 million people die because of cardiovascular diseases, cancer, diabetes, and infectious diseases (including HIV, Tuberculosis, and foodborne illnesses). The majority of people dying of these health conditions live in low- to mid-income countries with less access to advanced medical diagnostic tools. Low-cost, portable biosensors can offer unprecedented opportunities for realization of point-of-care diagnostics that are accessible to a broader population. In addition, among the grand challenges of the 21st century, the antibiotic-resistance of pathogenic bacteria poses a serious threat to the global health. Rapid detection of bacteria and subsequent prescription of the required dosage of antibiotics are critical for timely treatment of bacterial infections and slow down the emergence of antibiotic resistance. Conventional antibacterial testing systems are usually slow or expensive. Therefore, faster and more accessible methods are highly desirable. To approach both problems, we need to develop low-cost, rapid bioanalysis tools that are also accurate and allow multiplexed screening. Towards this goal, we developed a low-cost, array-formatted electrochemical sensor for rapid detection and on-chip analysis of biomolecules, including DNA and bacteria. The method utilizes droplet evaporation to concentrate the analyte and reduces the detection time from days to mere minutes. We conducted a comprehensive analysis of different parameters affecting the sensor performance, all supported by a physics-based framework. This work demonstrates the power of time-dependent electrical analysis to sort live and dead bacterial cells in only a few minutes as well as on-chip probing of some of their fundamental behaviors in response to important environmental triggers, in particular, osmotic stress, heat, and antibiotics. These findings highlight the potential of electrochemical biosensors which in tandem with the advances in microfluidics and material processing can create next generation of low-cost, real-time biological interrogation systems
An Aqueous Route to Oxygen-Deficient Wake-Up-Free La-Doped HfO2 Ferroelectrics for Negative Capacitance Field Effect Transistors
Full text linkThe crucial role of nanocrystalline morphology in stabilizing the ferroelectric orthorhombic (o)-phase in doped-hafnia films is achieved via chemical solution deposition (CSD) by intentionally retaining carbonaceous impurities to inhibit grain growth. However, in the present study, large-grained (>100 nm) La-doped HfO2 (HLO) films are grown directly on silicon by adopting engineered water-diluted precursors with a minimum carbonaceous load and excellent shelf life. The o-phase stabilization is accomplished through a well-distributed La dopant, which generates uniformly populated oxygen vacancies, eliminating the need for oxygen-scavenging electrodes. These oxygen-deficient HLOs show a maximum remnant polarization of 37.6 μC/cm2 (2Pr) without wake-up and withstand large fields (>6.2 MV/cm). Furthermore, CSD-HLO in series with Al2O3 improves switching of MOSFETs (with an amorphous oxide channel) based on the negative capacitance effect. Thus, uniformly distributed oxygen vacancies serve as a standalone factor in stabilizing the o-phase, enabling efficient wake-up-free ferroelectricity without the need for nanostructuring, capping stresses, or oxygen-reactive electrodes
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