1,721,016 research outputs found
Current mode filter structure based on dual output transconductance amplifiers
No full textA new current mode filter structure based on the dual output OTA is described. By appropriate choice of components, the structure provides lowpass, highpass, and bandpass responses. Experimental results which confirm the theoretical analysis are given
Improved Data Compression for Serial Interconnected Network on Chip through Unused Significant Bit Removal
No full text
Power-Aware Design Method for Class-A Switched-Current Wave Filters
No full textThis paper addresses power consumption in switched-current filters, designed using the wave filter technique and Class-A memory cells. It has been demonstrated that power consumption can be reduced through the proposed two stage bias and signal current scaling method, whilst ensuring no degradation in the filters total harmonic distortion. Two full transistor-level filter case studies using 0.6mm 3.3V BSim3v3 CMOS foundry models are given to demonstrate the method, with additional simulation results for filters of different types and orders showing power savings as high as 16.6%. One case study has been fabricated, with measured silicon results confirming power savings using the proposed method
A New BIST Methodology for Fully-Balanced OTA-C Filters
No full textAbstract - This paper proposes a new BIST structural testing methodology for fully-balanced OTA-C filters. The methodology is based on using a simple group-delay equaliser to emulate the function of the filter under test; any discrepancies resulting from comparing the filter and equaliser outputs indicates a faulty circuit. The test circuitry is designed using detailed analysis of the possible faults and their effects on the filter output, ensuring high fault coverage and minimisation of test accuracy dependence on manufacturing process variations. Furthermore, most of the test circuitry is digital, the analogue part requires only a single low-precision capacitor, and the frequency of the test stimulus does not need to be exact. Using simulation it has shown been that up to 98.6% fault coverage is possible when the proposed methodology is applied to a 4.5MHz Chebyshev low pass filter used as a test vehicle. The complete CMOS design of the self-testable filter is included. From actual layout, the estimated test circuitry area overhead is 20% which compares well with recently reported results
A CAD Methodology for Switched Current IP Cores
No full textAs system chips begin to absorb analog functionality there is increasing interest into what makes a good analog IP core. Research suggests that a solution could be the transistor-only switched current analog circuit technique, perfectly suited to modern digital processes. However, many designers are unfamiliar with this technology, favouring more conventional approaches not hindered by a lack of supporting CAD tools. To address this problem we have developed a CAD methodology, which allows rapid generation of switched current analog IP cores. This recently developed system has already shown good success with filter design and is being expanded to include other major analog functions
Analogue Filter IP Cores for Design Reuse
No full textThis paper addresses important considerations concerning the design of analogue filters, to ensure their suitability for use in a system on chip environment as intellectual property filter cores. We argue that switched-current is the most suitable circuit design technique and furthermore that the wave filter design methodology is favourable over an integrator approach. To speed up the design process some level of automation is clearly necessary and a system implemented in the SKILL language and within the Cadence Design Framework is particularly attractive given the access to powerful circuit analysis tools. A design flow is presented encompassing all of these attributes
Addressing Useless Test Data in Core-Based System-on-a-Chip Test
No full textThis paper analyzes the test memory requirements for core-based systems-on-a-chips and identifies useless test data as one of the contributors to the total amount of test data. The useless test data comprises the padding bits necessary to compensate for the difference between the lengths of different chains in multiple scan chains designs. Although useless test data does not represent any relevant test information, it is often unavoidable, and it leads to the trade-off between the test bus width and the volume of test data in multiple scan chains-based cores. Ultimately this trade-off influences the test access mechanism design algorithms leading to solutions that have either short test time or low volume of test data. Therefore, in this paper, a novel test methodology is proposed, which by dividing the wrapper scan chains into two or more partitions, and by exploiting automated test equipment memory management features reduces the useless memory. Extensive experimental results using ISCAS89 and ITC02 benchmark circuits are provided to analyze the implications of the number of wrapper scan chains in the partition, and the number of partitions on the proposed methodology
Testability Trade-offs for BIST RTL Data Paths: The Case for Three Dimensional Design Space
No full textThis paper focuses on BIST for RTL data paths and discusses testability trade-offs in terms of test application time, BIST area head, and power dissipation. Using a complex validation flow and experimental data for over 30,000 testable data paths, it is shown how test application time decreases asymtotically when increasing power constraints. Further, it is experimentally demonstrated why power conscious test synthesis and test scheduling algorithms are required due to large variations in useless power dissipation as test application time decreases. Finally, while previous research has outlined that test application time decreases as BIST area overhead increases, this paper shows that in order to reach high quality solutions in terms of test application time and BIST area overhead under given power constraints, a three dimensional design space needs to be explored
Power-Conscious Design Methodology for Class-A Switched-Current Wave Filters
No full textThis paper addresses power consumption in switched-current filters, designed using the wave filter technique and Class-A memory cells. It has been demonstrated that power consumption can be reduced through the proposed two stage bias and signal current scaling method, whilst ensuring no degradation in filter total harmonic distortion. Two full transistor-level filter case studies using 0.6µm 3.3V BSim3v3 CMOS foundry models are given to demonstrate the method, with additional simulation results for filters of different types and orders showing power savings as high as 16.6%. One case study has been fabricated, with measured silicon results confirming simulated savings
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