1,721,113 research outputs found
Power Conscious Test Synthesis and Scheduling
No full textPrevious research has outlined that power dissipated during test application is substantially higher than during functional operation, which leads to loss of yield and decreases reliability. This paper shows for the first time how power is minimized in BIST RTL data paths by using power conscious test synthesis and test scheduling. According to the necessity for achieving the required test efficiency power dissipation is classified into necessary and useless power dissipation. According to the occurrence during the testing process power dissipation is classified into test application and shifting power dissipation. The effect of test synthesis and scheduling on power dissipation is analyzed and power minimization is achieved in two steps. Firstly, during the testable design space exploration only power conscious test synthesis moves are accepted leading to minimization of useless power dissipation. Secondly, module selection during power conscious test scheduling satisfies power constraints while reducing test application time. Experimental results show savings up to 28% in test application power dissipation and up to 29% in shifting power dissipation
IEE Proceedings: Computers and Digital Techniques Special issue on "Design and Test Conference in Europe", DATE 03
No full textEditorial Special Issue on DATE03 Design and Test in Europe (DATE) is the main European conference that addresses all topics of research into technologies for electronic and embedded systems engineering. This covers design (hardware and embedded software), verification and test, algorithms and tools for design automation of electronic circuits and systems for wireless communications, multimedia and automotive systems. This Special Issue of IEE Proceedings Computers & Digital Techniques presents extended versions of selected papers from the 6th DATE conference held from 3-7 March 2003 in Munich, Germany. From the 152 papers presented, the executive and technical program committees selected 14 papers that received high grades in the review process for inclusion in this special issue. The authors of 12 papers accepted the invitation and submitted extended versions of their manuscript for peer-reviewing. These papers provide a good cross section of topics covered at DATE 03. The first five papers address “design methods”, including reconfigurable computing, power-aware system and circuit level design, asynchronous design, and networks on chip. The sixth, seventh, eighth, ninth and tenth papers address “CAD tools”, including synthesis of distributed embedded systems, transformation-based formal system design, high level synthesis, and interconnect modelling. The final two papers address “test”, including delay testing and low cost SoC test. The 12 papers are summarised in greater detail below. The first paper, Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling, by Mei et al., describes a modulo scheduling algorithm capable of exploiting loop-level parallelism in coarse-grained reconfigurable architectures, and proposes a graph presentation to model coarse-grained architectures. The algorithm is capable of placing, scheduling and routing operations simultaneously in a modulo-constrained 3D space, and it is evaluated using different tested kernels. The second paper, Scheduling and Mapping of Conditional Task Graph for the Synthesis of Low Power Embedded Systems, by Wu et al., addresses energy minimization in data/control dominated distributed embedded systems using dynamic voltage scaling (DVS). Novel DVS and genetic-based mapping techniques are described, and it is shown that a significant reduction in system energy dissipation is possible when compared with approaches that neglect the availability of DVS. The third paper, Masking the Energy Behaviour of DES Encryption”, by Saputra et al., considers the masking of energy consumption of the Data Encryption Standards algorithm by augmenting the instruction set architecture of a 32-bit processor used in smart cards with secure instruction. To support the secure operations, the necessary modifications to the processor architecture and instruction op-codes are outlined. The effectiveness of the augmented approach is demonstrated by simulation and comparison with existing approaches. The fourth paper, Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design, by Madalinski et al., tackles coding conflicts in Signal Transition Graphs (STGs) used for asynchronous control circuit behavior description. A visualization framework is proposed aimed at facilitating the manual refinement of an STG with complete state coding conflicts (i.e. conflicting cores). Two case studies are included to demonstrate the proposed framework. The fifth paper, Trade Offs in the Design of a Router with Both Guaranteed and Best Effort Services for Networks on Chip, by Rijpkema et al., addresses the problem of managing the design of complex chips by decoupling computation and communication. A router-based NoC architecture that combines guaranteed and best-effort services is proposed and a discussion of the important design issues (trade offs between complexity and efficiency) of such a router is presented. A CMOS prototype of the proposed router is also described. The sixth paper, Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems, by Pop et al., addresses the analysis and optimization of heterogeneous time-triggered and event-triggered systems implemented on multi-cluster embedded networks. Optimization heuristics for system synthesis are proposed, and validated using extensive experimental results including a real-life example. The seventh paper, Development and Application of Design Transformations in ForSyDe, by Sander et al., focuses on the development of a formal system design as an effective methodology for complex systems. The methodology is based on transformational design refinement, the formal basis of the transformations is discussed, and the benefits of transformations are illustrated through the design of an eighth-order FIR filter. The eight paper, Behavioural Specification Allocation to Minimize Bit Level Waste of Functional Units, by Molina et al., addresses the problem of hardware waste in high level synthesis, and proposes an allocation algorithm that minimizes this waste. The algorithm efficiency is demonstrated by extensive experimental results and comparative study with a current approach. The ninth paper, Dynamically Increasing the Scope of Code Motions During High-Level Synthesis of Digital Circuits, by Gupta et al., discusses improving the quality of control-intensive (nested conditionals and loops) high-level synthesis results by proposing dynamic conditional branch balancing technique. Two real-life multimedia and image processing applications are presented to demonstrate the effectiveness of the technique. The tenth paper, Modelling and Evaluation of Substrate Noise Induced by Interconnects, by Martorell et al., investigates the importance of interconnects as a source of substrate noise, and proposes a model for noise coupling between integrated signal interconnects and silicon substrate. The model accuracy is checked against real measured data obtained from 0.35?m test structures. The eleventh paper, Delay Defect Diagnosis Based Upon Statistical Timing Models – The First Step, by Krstic et al., addresses delay testing in deep sub-micron technology, proposes new delay defect diagnosis concepts, and shows how they compare with traditional logic detect diagnosis. Different diagnosis algorithms are described and evaluated using statistical defect injection and delay fault simulation. Finally, in the twelfth paper, Low Cost Software Based Self Testing of RISC Processor Cores, by Kranitis et al., the authors tackle the cost (development and tools) of testing processor cores and present a software-based self-testing methodology that supports low-speed and low-cost external testers. The methodology is validated by designing and testing a RISC processor. The guest editors would like to thank the DATE Executive Committee for supporting the development of this special issue, and would also like to thank April Sparks, Linda Meller and Stuart Govan at the IEE for their assistance in producing this issue. We would also like to sincerely thank all the authors for submitting their papers and the reviewers for keeping up with the very tight schedule that allowed us to complete this special issue as planned in less than seven months. We hope you enjoy this selection of some of the best papers from DATE 03. NORBERT WEHN University of Kaiserslautern, Germany Microelectronic System Design Research Group BASHIR M AL-HASHIMI University of Southampton, UK Electronic System Design Grou
Power Minimisation Techniques for Testing Low Power VLSI Circuits
No full textPower dissipation has become a significant concern in deep submicron VLSI and a substantial amount of research has been conducted in order to develop power minimisation techniques. While many techniques have investigated power minimisation during the functional mode of operation, an emerging research area is power minimisation during testing. Power minimisation during test application is important since it increases yield and reliability. This paper presents a review of power minimisation techniques for testing low power VLSI circuits recently proposed by the authors
Modified Isolation Rings for Parallel Test Access in Core Based SoC
No full textOne of the major issues in implementing core-based systems on a chip (SoC) is testing of cores. This paper presents a method to add parallel test access to cores within the SoC for speeding up the system testing time. This involves the introduction of multiple insertion and extraction points in the existing isolation ring of the core and performing the functions of shifting and bypassing simultaneously. To compute the gain in overall testing time ring parameters are introduced and an example demonstrating the efficiency of the proposed method is given
Power-conscious test synthesis and scheduling
No full textBIST increases circuit activity and hence power in data path circuits. The voltage drop that occurs during testing causes some good circuits to fail the testing process, leading to unnecessary manufacturing yield loss. Addressing this problem, the authors show how test synthesis and scheduling affect power dissipation and present new power-conscious algorithms
Considering Power Variations of DVS Processing Elements for Energy Minimisation in Distributed Systems
No full textDynamic voltage scaling (DVS) is a powerful technique to reduce power dissipation in embedded systems. Some efficient DVS algorithms have been recently proposed for the energy reduction in distributed system. However, they achieve the energy savings solely by scaling the system task with respect to the timing constraints, while neglecting that power varies among the tasks executed by DVS processing elements (DVS-PEs). In this paper we investigate the problem of considering DVS-PE power variations dependent on the executed tasks, during the synthesis of distributed embedded systems and its impact on the energy savings. Unlike previous approaches, which minimise the energy consumption by exploiting the available slack time without considering the PE power profiles, a new and fast heuristic for the voltage scaling problem is proposed, which improves the voltage selection for each task dependent on the individual power dissipation caused by that task. Experimental results show that energy reductions with up to 80.7% are achieved by integrating the proposed DVS algorithm, which considers the PE power profiles, into the co-synthesis of distributed systems
Low Power Process Assignment for Distributed Embedded Systems using Dynamic Voltage Scaling
No full textThis paper presents an efficient algorithm for voltage scaling of an distributed embedded system taking communicating processes into account. The algorithm finds scaled voltages for each processes without restricting the applicable voltage levels apriori. In addition the algorithm is not limited by a fixed power consumption among processes. Furthermore we show the importance of a process optimisation which is optimised for the dynamic voltage scaling (DVS) technique. Various examples from the literature and randomly generate show the efficiency of the proposed scaling algorithm and the DVS optimised process assignment
Dual Transitions Petri Net based Modelling Technique for Embedded Systems Specification
No full textThis paper presents a new modelling technique capable of modelling both control and data information using a single unified approach. This is achieved by modifying the classical Petri Net structure, allowing it to have two types of transitions and arcs. As a consequence, loops and conditional operations within complex specifications are easily identified. The system dynamic behaviour is modelled using a new marking scheme of the net consisting of a new element called "value" for data representation in addition to classical tokens used for control purpose. Structural definitions, behavioural rules and graphical representation of the new modelling technique are given. One potential application of the proposed modelling technique is the internal representation of embedded systems specification. Two examples are included illustrating the applicability and efficiency of the proposed modelling technique
Comparative Reliability Analysis between AMBA and Network-on-Chip: An MPEG-2 Case Study
No full textWe present comparative reliability analysis between shared-bus AMBA and network-on-chip (NoC) in the presence of single-event upsets (SEUs) using MPEG-2 video decoder as a case study. Employing SystemC-based cycle-accurate fault simulations, we investigate how the decoder reliability is affected when SEUs are injected into the computation cores and communication interconnects of the decoder. We show that for a given soft error rate, AMBA-based decoder experiences higher SEUs during computation due to higher execution time. On the other hand, NoC-based decoder experiences higher SEUs during inter-core communication due to higher channel latency and resource usage in the interconnects. Furthermore, we evaluate the impact of total SEUs at application-level for NoC- and AMBA-based decoders
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