1,721,364 research outputs found
Supplemental data of A High-Throughput FPGA Architecture for Joint Source and Channel Decoding
No full textData for the paper Brejza, Matthew, Maunder, Rob, Al-Hashimi, Bashir and Hanzo, Lajos (2016) A high-throughput FPGA architecture for joint source and channel decoding. IEEE Access (10.1109/ACCESS.2016.2633441)</span
A Scalable Turbo Decoding Algorithm for High-Throughput Network-on-Chip Implementation
No full textMatlab codes relating to the article Al-Dujaily, Ra'ed, Li, An, Maunder, Robert G, Mak, Terrence, Al-Hashimi, Bashir M. and Hanzo, Lajos (2016) A Scalable Turbo Decoding Algorithm for High-Throughput Network-on-Chip Implementation. IEEE Access.</span
Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits
No full textThis paper presents a new technique for power minimization during test application in sequential circuits using multiple scan chains. The technique is based on a new design for test architecture and a novel test application strategy which reduces spurious transitions in the circuit under test. To facilitate the reduction of spurious transitions, the proposed design for test architecture is based on classifying scan latches into compatible, incompatible and independent scan latches. Based on their classification, the scan latches are partitioned into multiple scan chains and a single extra test vector associated with each scan chain is computed. A new test application strategy which applies the extra test vector to primary inputs while shifting out test responses for each scan chain, minimizes power dissipation by eliminating the spurious transitions which occur in the combinational part of the circuit. The newly introduced multiple scan chain-based technique does not introduce performance degradation and minimizes clock tree power dissipation with minimal impact on both test area and test data overhead. Unlike previous approaches which are test set dependent and, hence, are not able to handle large circuits due to the complexity of the design space, this paper shows that with low test area and test data overhead substantial savings in power dissipation during test application are achieved in very low computational time for both small and large test sets. For example, in the case of the benchmark circuit s15850 it takes <600s in computational time and <1 percent in test area and test data overhead to achieve over 80 percent savings in power dissipation
Simultaneous scheduling, allocation and binding in high level synthesis
No full textThe authors describe a new and efficient algorithm for concurrent scheduling, allocation and binding in high level synthesis (HLS). Globally optimum data path realisations with efficient single-level interconnect structures are rapidly obtained using a novel strategy for the generation of new synthesis solutions applied to simulated annealing. An example of a fifth-order wave digital filter is included
'Switched-Current Wave Group Delay Equalizers'
No full textTo improve the elliptic filters step response, group delay equalizers are often cascaded with the filters. This paper describes the design of switched-current (SI) group delay equalizer using wave synthesis technique. This design is based on a new all-pass circuit, where the poles are generated using wave structures. Simulation results are included demonstrating that the 3rd-order SI group delay equalizer can reduces the amount of overshoot in 100kHz elliptic low-pass filter step response by 50%. This is as a result of reducing the filter group delay variation from 2.29us to 0.32us when the group delay equalizer is employe
Synthesis of switched-current Ladder Derived Group delay Equalizers
No full textThis paper describes the design of switched-current group delay equalizers. The design process is based on the pole-zero mirroring technique; with equalizer z-transfer functions generated using an optimization algorithm. To facilitate the systematic implementation of the equalizers, a model describing the design process is developed. A novel feature of the equalizers implementation is that wave structures are employed in realizing the equalizer poles instead of integrators. MATLAB and SI simulation results based on a 6th-order equalizer are included. The results demonstrate that the equalizer can reduce the delay of a 5th-order, 1MHz lowpass SI elliptic filter from 155ns to <20ns over the entire filter bandwidth
Dataset supporting the article entitled "Energy-Driven Computing: Rethinking the Design of Energy Harvesting Systems"
No full textThis dataset supports the article entitled "Energy-Driven Computing: Rethinking the Design of Energy Harvesting Systems" accepted for publication in DATE 2017.</span
Low Power Testing of Digital ICs: Overview
No full textThis paper presents an overview of low power testing of digital ICs and show why traditional DFT techniques are not suitable for low power VLSI circuits with the help of examples. The paper reviews some of the recently proposed work for lowering power during test including the work at Southampton in terms of scan based and RTL datapath power dissipation
- …
