1,720,989 research outputs found
Power-Aware Design Method for Class-A Switched-Current Wave Filters
No full textThis paper addresses power consumption in switched-current filters, designed using the wave filter technique and Class-A memory cells. It has been demonstrated that power consumption can be reduced through the proposed two stage bias and signal current scaling method, whilst ensuring no degradation in the filters total harmonic distortion. Two full transistor-level filter case studies using 0.6mm 3.3V BSim3v3 CMOS foundry models are given to demonstrate the method, with additional simulation results for filters of different types and orders showing power savings as high as 16.6%. One case study has been fabricated, with measured silicon results confirming power savings using the proposed method
A New BIST Methodology for Fully-Balanced OTA-C Filters
No full textAbstract - This paper proposes a new BIST structural testing methodology for fully-balanced OTA-C filters. The methodology is based on using a simple group-delay equaliser to emulate the function of the filter under test; any discrepancies resulting from comparing the filter and equaliser outputs indicates a faulty circuit. The test circuitry is designed using detailed analysis of the possible faults and their effects on the filter output, ensuring high fault coverage and minimisation of test accuracy dependence on manufacturing process variations. Furthermore, most of the test circuitry is digital, the analogue part requires only a single low-precision capacitor, and the frequency of the test stimulus does not need to be exact. Using simulation it has shown been that up to 98.6% fault coverage is possible when the proposed methodology is applied to a 4.5MHz Chebyshev low pass filter used as a test vehicle. The complete CMOS design of the self-testable filter is included. From actual layout, the estimated test circuitry area overhead is 20% which compares well with recently reported results
A CAD Methodology for Switched Current IP Cores
No full textAs system chips begin to absorb analog functionality there is increasing interest into what makes a good analog IP core. Research suggests that a solution could be the transistor-only switched current analog circuit technique, perfectly suited to modern digital processes. However, many designers are unfamiliar with this technology, favouring more conventional approaches not hindered by a lack of supporting CAD tools. To address this problem we have developed a CAD methodology, which allows rapid generation of switched current analog IP cores. This recently developed system has already shown good success with filter design and is being expanded to include other major analog functions
Analogue Filter IP Cores for Design Reuse
No full textThis paper addresses important considerations concerning the design of analogue filters, to ensure their suitability for use in a system on chip environment as intellectual property filter cores. We argue that switched-current is the most suitable circuit design technique and furthermore that the wave filter design methodology is favourable over an integrator approach. To speed up the design process some level of automation is clearly necessary and a system implemented in the SKILL language and within the Cadence Design Framework is particularly attractive given the access to powerful circuit analysis tools. A design flow is presented encompassing all of these attributes
Testability Trade-offs for BIST RTL Data Paths: The Case for Three Dimensional Design Space
No full textThis paper focuses on BIST for RTL data paths and discusses testability trade-offs in terms of test application time, BIST area head, and power dissipation. Using a complex validation flow and experimental data for over 30,000 testable data paths, it is shown how test application time decreases asymtotically when increasing power constraints. Further, it is experimentally demonstrated why power conscious test synthesis and test scheduling algorithms are required due to large variations in useless power dissipation as test application time decreases. Finally, while previous research has outlined that test application time decreases as BIST area overhead increases, this paper shows that in order to reach high quality solutions in terms of test application time and BIST area overhead under given power constraints, a three dimensional design space needs to be explored
Power-Conscious Design Methodology for Class-A Switched-Current Wave Filters
No full textThis paper addresses power consumption in switched-current filters, designed using the wave filter technique and Class-A memory cells. It has been demonstrated that power consumption can be reduced through the proposed two stage bias and signal current scaling method, whilst ensuring no degradation in filter total harmonic distortion. Two full transistor-level filter case studies using 0.6µm 3.3V BSim3v3 CMOS foundry models are given to demonstrate the method, with additional simulation results for filters of different types and orders showing power savings as high as 16.6%. One case study has been fabricated, with measured silicon results confirming simulated savings
NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating
Full text linkIn this paper we show that power gating techniques become more effective during their lifetime, since the aging of sleep transistors (STs) due to negative bias temperature instability (NBTI) drastically reduces leakage power. Based on this property, we propose an NBTI and leakage aware ST design method for reliable and energy efficient power gating. Through SPICE simulations, we show lifetime extension up to 19.9x and average leakage power reduction up to 14.4% compared to standard STs design approach without additional area overhead. Finally, when a maximum 10-year lifetime target is considered, we show that the proposed method allows multiple beneficial options compared to a standard STs design method: either to improve circuit operating frequency up to 9.53% or to reduce ST area overhead up to 18.4%
Impact of Multicycled Scheduling on Power-Area Tradeoffs in Behavioural Synthesis
No full textMulticycling is a widely investigated technique for performance optimisation in behavioural synthesis. It allows an operation to execute over two or more control steps with the aim of increasing the performance and/or minimising the power consumption. This paper presents a new time-constrained scheduling (TCS) algorithm that takes into account the combined influence of clock period and the multicycled functional units execution time on the quality of the schedules in terms of power and area. It is shown that it is possible to produce a set of solutions that have similar power consumptions, however differ in terms of resource requirements, yet meeting the imposed real-time constraint. Furthermore, extensive experiments on behavioural benchmarks show that the proposed approach is capable of obtaining schedules with single supply domain that have identical resource requirements and comparable power consumption to schedules obtained using multiple supply voltages, further reducing the design complexity
Analysis of mirror mismatch and clock-feedthrough in Bruton transformation switched current wave filters
No full textThe paper describes the modelling and analysis of the non-ideal performance of recently introduced Bruton transformation switched current (SI) wave filters. Two sources of errors are considered: mismatching in current mirrors and clock-feedthrough in delay cells. Using transistor-level realisations, analytical non-ideal models for the main components of Bruton transformation wave fillers are developed, including capacitive source and load, and frequency dependent negative resistors. These models are integrated with MATLAB to study the influence of these errors on the filter frequency response. The non-ideal performance of 3rd-order low-pass and 5th-order high-pass elliptic filters using second-generation and S2l delay cells are analysed and included.</p
BTI aware thermal management for reliable DVFS designs
Full text linkIn this paper, we show that dynamic voltage and frequency scaling (DVFS) designs, together with stress-induced BTI variability, exhibit high temperature-induced BTI variability, depending on their workload and operating modes. We show that the impact of temperature-induced variability on circuit lifetime can be higher than that due to stress and exceed 50% over the value estimated considering the circuit average temperature. In order to account for these variabilities in lifetime estimation at design time, we propose a simulation framework for the BTI degradation analysis of DVFS designs accounting for workload and actual temperature profiles. A profile is generated considering statistically probable workload and thermal management constraints by means of the HotSpot tool. Using the proposed framework we explore the expected lifetime of the ethernet circuit from the IWLS05 benchmark suite, synthesized with a 32nm CMOS technology library, for various thermal management constraints. We show that margin-based design can underestimate or overestimate lifetime of DVFS designs by up to 67.8% and 61.9%, respectively. Therefore, the proposed framework allows designers to select appropriately the dynamic thermal management constraints in order to tradeoff long-term reliability (lifetime) and performance with upto 35.8% and 26.3% higher accuracy, respectively, against a temperature-variability unaware BTI analysis
- …
