1,721,092 research outputs found
Comparative Evaluation of Layout Density in 3T, 4T and MT FinFET Standard Cells
No full textIn this paper, issues related to the physical design and layout density of FinFET standard cells are discussed. Analysis significantly extends previous analyses, which considered the simplistic case of a single FinFET device or extremely simple circuits. Results show that analysis of a single device cannot predict the layout density of FinFET cells, due to the additional spacing constraints imposed by the standard cell structure.
Results on the layout density of FinFET standard cell circuits are derived by building and analyzing various cell libraries in 32-nm technology, based on 3T and four-terminal (4T) devices, as well as on the recently proposed cells with mixed 3T-4T devices (MT). The results obtained for spacer- and lithography-defined FinFETs are observed from the technology scaling perspective by also considering 45-nm and 65-nm libraries. The effect of the fin and cell height on the layout density is studied.
Results show that that 3T and MT FinFET standard cells can have the same layout density as bulk cells (or better) for low (moderate) fin heights. Instead, 4T standard cells have an unacceptably worse layout density. Hence, MT standard cells turn out to be the only viable option to apply back biasing in FinFET standard cell circuits
Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial
No full textIn this paper, the state of the art in ultra-low power (ULP) VLSI design is presented within a unitary framework for the first time. Few general principles are first introduced to gain an insight into the design issues and approaches that are specific to ULP systems, as well as to better understand the challenges that have to be faced in the foreseeable future. Intuitive understanding is accompanied by rigorous analysis for each key concept. The analysis ranges from the circuit to the micro-architectural level, and reference is given to process, physical and system levels when necessary.
Among the main goals of this paper, it is shown that many paradigms and approaches borrowed from traditional above-threshold VLSI design are actually incorrect. Accordingly, common misconceptions in the ULP domain are debunked and replaced with technically sound explanations
Understanding DC Behavior of Subthreshold CMOS Logic through Closed-Form Analysis
No full textIn this paper, the DC behavior of subthreshold CMOS logic is analyzed in a closed form for the first time in the literature. To this aim, simplified large-signal and small-signal models of MOS transistors in subthreshold region are first developed. After replacing transistors with these equivalent models, analysis of the main DC parameters of CMOS logic gates is performed. In particular, the change in the DC characteristics shape due to operation at ultra-low voltages is analyzed in detail, evaluating analytically the degradation in the logic swing, the symmetry and the steepness of the transition region, as well as the change in the unity-gain points position. The resulting expressions permit to gain an insight into the basic dependencies of DC behavior on design and device parameters.
The noise margin is explicitly evaluated and modeled with a very simple expression. Interestingly, analysis shows that the noise margin deviates from the ideal half-swing value by an amount that linearly depends on the logarithm of the pn-ratio. Analysis permits to evaluate the minimum supply voltage that ensures correct operation of CMOS logic (i.e., positive noise margin). Previously proposed rule of thumbs to evaluate minimum voltage are also theoretically justified. Moreover, the impact of PMOS/NMOS unbalancing on DC characteristics is analyzed from a design perspective. Considerations on the impact of process/voltage/temperature variations are also introduced. Results are validated through extensive simulations in a 65-nm CMOS technology
Analysis of Layout Density in FinFET Standard Cells and Impact of Fin Technology
No full textIn this paper, the layout density of three-terminal FinFET logic circuits is extensively analyzed. As opposite to previous works, which are focused either on single devices or simplistic circuits, this analysis explicitly includes the geometric constraints that are imposed by the standard cell approach. The impact of the fin technology is analyzed by comparing the lithography- and spacer-defined approaches, as well as evaluating the dependence of layout density on the fin height.
Results show that FinFET standard cells have a layout density that is better than bulk cells even for moderately tall fins. The fin height is also shown to be a powerful knob to improve the layout density in FinFET cells. Analysis also shows that the usually claimed 2X density improvement of the spacer-defined technology compared to the lithography-defined is dramatically reduced in real standard cells, and can be negligible for tall fins. All results are justified through considerations at the physical level of abstraction. Various versions of a 32-nm 44-gate library are laid out to carry out the analysis
Very Fast Carry Energy Efficient Computation based on Mixed Dynamic/Transmission-Gate Full Adders
No full textA circuit approach based on the adoption of mixed dynamic and transmission-gate Full Adder topologies to achieve very fast computation in carry chains is discussed. From a design point of view, the approach is very simple and permits to exceed the speed performance of fast domino logic by more than 30% without degrading the energy efficiency. Post-layout simulations on a 90-nm CMOS technology are presented to validate the results
Modeling strategies of the input admittance of RC interconnects for VLSI CAD tools
No full textIn this paper, models of the input admittance of RC interconnects are discussed in depth to understand and evaluate their loading effects on the driving CMOS gates. From the detailed analysis of the input admittance pole-zero location, arguments are derived to prove that their input admittance can be accurately approximated to that of a low-order equivalent RC circuit, in contrast to the case of timing analysis of RC wires. More specifically, 1st- or 2nd-order equivalent circuits are derived analytically via the moment matching approach, as opposite to previous analyses that rely on purely numerical approaches. Moreover, simple analytical rules to extend results to arbitrarily complex networks are derived, as opposite to the usual approach that requires the numerical estimation of moments. Being fully analytical, the proposed approach permits to develop models that are extremely simple (i.e., computationally efficient), as well as to gain an insight into the properties of the input admittance of RC interconnects.
The proposed equivalent circuits are evaluated and validated in situations that occur in real CAD design flows, where RC wire loading effects are estimated by CAD tools to perform the timing/power analysis of the buffer driving the wire. The analysis is validated through extensive simulations on a 65-nm CMOS technology. Well-defined criteria are also derived to select the appropriate model of the RC wire input admittance for accurate timing/power estimations in VLSI CAD tools
NAND/NOR Adiabatic Gates: Power Consumption Evaluation and Comparison versus the Fan-In
No full textIn the paper the buffer and the NAND/NOR adiabatic gate are compared with that designed with the traditional CMOS approach. The comparison is made both assuming an assigned power supply and setting its value to minimize the power consumption. General relationship independent from process parameter, which are also simple to be useful in a pencil-and-paper evaluation, are carried out.
Analytical results are validate with Spice Simulations by using 0.8-m CMOS technology. The analysis show that with the considered technology and a fan-out of three, the adiabatic buffer is advantageous for frequency lower than 167 MHz and 21 MHz for the non optimized and the optimized design, respectively. These frequencies lower to 23 MHz and 1.3 MHz for the NAND/NOR gate. Moreover all the frequency reduce linearly increasing the fan out of the gate
A Simple Strategy for Optimized Design of One-Level Carry-Skip Adders
No full textIn this paper a novel strategy to design Carry Skip Adders is proposed. It allows to distribute bits into groups to achieve minimum delay, and consists of two steps. The first is a preliminary analytical sizing based on timing considerations, the second is a successive refinement to achieve the desired number of bits. The strategy is simple, systematic and general, thus it is helpful to design in a pencil-and-paper approach, as well as providing an in-depth understanding of the optimum group sizing. Moreover, it allows to analytically estimate the minimum delay achievable before carrying out the design.
The strategy proposed has been validated by applying it to the design of more than 50 adders, varying delay of logic gates used and number of bits. Analysis confirms that the strategy provides minimum delay in practical cases
Power-Aware Design Techniques for Nanometer MOS Current-Mode Logic Gates: a Design Framework
No full textIn the last years, MOS Current-Mode Logic (MCML) circuits are gaining a remarkable interest in several VLSI applications, ranging from high-accuracy mixed-signal circuits to high-speed circuits for channel (de)multiplexing in optic fiber and Radio Frequency (RF) telecommunication systems. However, advantages over traditional CMOS logic are achieved at the cost of a static power consumption, which must be kept as low as possible. Accordingly, a conscious management of the power-delay trade-off is essential in the design of such circuits.
This paper presents several recent ideas on the design of digital MCML circuits organized in a comprehensive framework. The treatment reviews and extends previous results by incorporating Deep-Sub-Micron (DSM) effects from the beginning, with a strongly simplified analytical formulation to improve the understanding and to easy the design. Interesting properties and design criteria are derived from simple analytical models. From these models, a deep insight into the design of MCML circuits is gained, which is essential for both the efficient design of MCML cells and the development of an automated design flow. Numerical examples are presented by considering a 90-nm CMOS process
Oscillation Frequency in CML and ESCL Ring Oscillators
No full textAbstract—In this paper a model to accurately evaluate even in a pencil-and-paper manner the oscillation frequency of a ring oscillator
made up by a CML or ESCL differential gate is proposed. The model allows us to simply estimate the oscillation frequency changes due both to
the bias current change and to process tolerances.
The model was validated by Spice simulations on both 6- and 20-GHz technologies for the CML ring oscillator, and on 0.8- mCMOS process for
the ESCL ring oscillator. The estimated oscillation frequency agrees with the simulated one. Indeed, average errors lower than 10% were found
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