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An investigation of high level synthesis for computational hardware
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A New Structure for Datapath Synthesis
No full textFrom high level synthesis point of view, target design can be divided into two parts: controller and datapath. Single shared bus is a suitable structure for datapath synthesis regarding interconnections costs which suffers from several drawbacks such as its low data communication bandwidth. It has also been shown that the word-length of functional units has a great impact on design costs. A combination of both methods is the core idea of this paper which is offering an improved communication structure. In this method datapath is partitioned into groups connected to segmented shared buses and every partition has a different width and all the functional units connected to a bus partition have the same input/output word-lengths. Having controlled the group binding and word-length of the functional units, as well as the other synthesis parameters, a high-level synthesis tool is introduced to implement DSP algorithms in digital hardware. The tool uses a multi-objective optimization genetic algorithm to minimize the circuit area, delay, power consumption and digital noise by selecting optimal grouping and word-length for the shared bus structure. Results demonstrate that savings can be made in the overall system costs by applying this method
MW²P-Bus: A New Bus Structure for Datapath Synthesis
No full textDatapath optimisation has a great impact on the efficiency of computationally intensive embedded designs such as DSP blocks. Bus-oriented design is one of the low cost approaches to datapath synthesis but which suffers from a low data communication bandwidth %uniformly provided for all the connected units. It has been shown, on the other hand, that the word-length of functional units has a great impact on design costs. A combination of both methods is the core idea of this paper by offering an improved bus-oriented structure for datapath synthesis. In this method a datapath is partitioned into groups which are connected to a set of shared buses. Every bus segment has a different width and all the functional units connected to a bus segment have the same word-length. Having controlled the group binding and word-length of the functional units, as well as the other synthesis parameters, a high-level synthesis tool is introduced to implement DSP algorithms in register transfer level specification. The tool uses a multi-objective optimization algorithm to minimize the circuit area, delay, power consumption and digital noise by selecting optimal grouping and word-length for the bus structure. Results demonstrate that 25% to 75% savings can be made in the latency cost by applying this method
Area Word-Length Trade off in DSP Algorithm Implementation and Optimization
No full textThis paper proposes a frame work for High Level Synthesis of DSP algorithms with emphasis on differences between DSP systems and other digital systems. Accordingly a multiple word length has been used to optimize the system digital noise and area trade off. Based on a proposed architecture, required cost function, synthesiser and optimizer and intermediate data bases have been introduced and implemented. Optimization has been done by an optimizer based on Genetic Algorith
Word-Length Oriented Multiobjective Optimization of Area and Power Consumption in DSP Algorithm Implementation
No full textThe word-length of Functional Units (FU) has a great impact on design costs. This paper addresses the problem of choosing different word-lengths for each FU while considering circuit area and power consumption. A high-level synthesis tool is used to minimize the circuit area and power consumption by selecting an optimal word-length for each FU in the system. Our results demonstrate that by customizing word lengths to nonstandard sizes, savings can be made in the overall area and power without losing accuracy
Tutela e Valorizzazione dei siti UNESCO in Iran: Una proposta metodologica per il piano di gestione di Naqshe Jahan
Get PDFThe policy of preservation of cities and monuments in Iran is going through a review process. The traditional formulas adopted till now are inadequate to ensure the integrity of the tangible and intangible values of the historical and artistic heritage present in Iran. UNESCO has drawn the attention to some iranian sites that are threatened with degradation and that, despite the recent recommendations contained in the Memorandum of Wien (2004) and in the Budapest’s Declaration (2002), some iranians sites are still lacking of a Management plan.
Analyzing the Management plans prepared till now in Iran, I noted that there is not a reference model and that the documents prepared are simple descriptive and iconographic texts that do not provide an action plan and a list of intervention aimed to protect and enhancing the sites.
Amoung the different UNESCO sites in Iran, I decided to analyze the most representative of the persians city: the 89600 square meters Naqshe Jahan complex, the first iranian site to be inscribed in the world heritage list in 1979 and the one able to show the historical evolution that Iran has experienced. Naqshe Jahan complex is situated in the ancient city of Isfahan, capital of the Safavid dynasty during the XVI century. The city is the most complete example of Persian city in which it is still possible to distinguish monuments and buildings dating back from different centuries, from the X, XIV and XVI century. The social and economical hart of the city is represented by the big square of Naqshe Jahan, built by Shah Abbas during in the 1590 and still considered the symbol of the whole city
A Modified Izhikevich Model For Circuit Implementation of Spiking Neural Networks
Get PDFThe Izhikevich neuron model reproduces the spiking and bursting behaviour of certain types of cortical neurons. This model has a second order nonlinearity that makes it difficult to implement in hardware. We propose a simplified version of the model that has a piecewise-linear relationship. This modification simplifies the hardware implementation but demonstrates similar dynamic behaviour
Fixed-point multiplication: a probabilistic bit-pattern view
No full textThe truncation error of fixed-point multiplication is commonly modelled as white noise with a uniform distribution. This paper shows the inaccuracy of this assumption by using a bitwise approach. A probabilistic bit-pattern analysis of the fixed-point multiplication is presented from which an accurate probability model for the truncation error is derived. Using this PDF model, exact values for the mean and variance of the truncation error in the output of the fixed-point multiplication are formulated for the first time. The proposed PDF model, mean and variance values are compact and usable in word-length optimization algorithms
Effect of Variability in SWCNT-Based Logic Gates
No full textThis work is concerned with Carbon Nanotube diameter variations and the resulting uncertainties on the behavior of logic gates made from Single Walled Carbon Nanotubes (SWCNTs). Monte Carlo simulations were performed for logic gates based on CNTs of different mean diameters using the Stanford CNFET model. Delay characteristics of logic gates (NOT, NAND, NOR) are studied. This work reveals that logic gates employing SWCNTs with mean diameters greater than about 1.2 nm, show less variation in their timing characteristics, provided that a CNT diameter standard deviation of less than 0.1nm can be guaranteed by a technology process
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