1,720,968 research outputs found
Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells
No full textLeakage estimation is an important step in nano-scale technology digital design flows. While reliable data exist on leakage trends with bulk CMOS technology scaling in stand-alone devices and circuits, there is a lack of public domain results on the effect of scaling on leakage power consumption for a complete standard cell set. We present an analysis on a standard cell library applying a logic-level estimation model, supported by SPICE BSIM4 comparison. The logic-level model speedup over SPICE is > 10(3) with average accuracy below 1% error. We therefore explore the effects of scaling on the whole standard cell set with respect to different leakage mechanisms (sub-threshold, body, gate) and to input pattern dependence. While body leakage appears to be dominant, sub-threshold leakage is expected to increase more than other components with scaling. Detailed data of the whole analysis are reported for use in further research on leakage aware digital design. (C) 2013 Elsevier Ltd. All rights reserved
A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs
No full textLogic-level estimators of leakage currents, in nanoscale standard-cell-based designs, are relevant for the dramatic speed advantage with respect to analog SPICE-level simulation. We propose a novel logic-level leakage estimation model based on the characterization of voltages at the internal nodes of digital cells, in conjunction with the characterization of leakage currents in a single field-effect transistor (FET) device and with the input-dependent Kirchhoff current law expression of the total current in the cell topology. The voltage-based nature of the approach simplifies the inclusion of supply voltage variation/scaling impact, as well as of output voltage drop (loading effect), on leakage currents. The method has been implemented in hardware description language models of a complete cell library. Exhaustive tests report average accuracy below 1% error in 22-nm CMOS and 20-nm FinFET technologies, when compared with SPICE BSIM simulation results
Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations
Full text linkWe present the detailed results of the application of mathematical optimization algorithms to transistor sizing in a full-adder cell design, to obtain the maximum expected fabrication yield. The approach takes into account all the fabrication process parameter variations specified in an industrial PDK, in addition to operating condition range and NBTI aging. The final design solutions present transistor sizing, which depart from intuitive transistor sizing criteria and show dramatic yield improvements, which have been verified by Monte Carlo SPICE analysis
Optimal transistor sizing for maximum yield in variation-aware standard cell design
No full textProcess variability, in addition to wide temperature and supply voltage variation ranges, severely degrades the fabrication outcome (yield) of digital cells as for the fulfillment of performance specification bounds. This paper presents the application of mathematical optimization to the design of standard cells that are robust to process variations even in worst-case operating conditions. The method attains the optimal sizing of individual transistors in the cell for maximizing the statistical yield referring to leakage power and propagation delay bounds, with local and global process variations specified by industrial process development kits (PDKs). The approach is demonstrated for a 40 nm low-power standard threshold voltage Complementary Metal Oxide Semiconductor (CMOS) technology, for an intended operating temperature range [−40 °C, 125 °C] and supply voltage range [0.95 V, 1.05 V]. The reported optimization results show a yield improvement from an initial 50% to 99.9%, and Simulation Program with Integrated Circuit Emphasis (SPICE)-level Monte Carlo analysis confirmed the estimated yield of the obtained circuits
Geometry scaling impact on leakage currents in FinFET standard cells based on a logic-level leakage estimation technique
No full textStatic power consumption is one of the most critical issues in CMOS digital circuits, and FinFET technology is being recognized as a valid solution for the problem. In this chapter, we utilize a logic-level leakage current estimation technique relying on an internal node voltage-based model. The model is implemented in the form of VHDL packages. By utilizing the capability of the model, the behavior of major leakage component has been analyzed separately for FinFET technology scaling over single- and multi-stage digital standard cells
A novel logic level calculation model for leakage currents in digital nano-CMOS circuits
No full textAccurate leakage current estimation in the early phase of digital IC synthesis is an increasingly critical step in the design flow. We present a logic-level estimation approach, suitable for implementation in HDL models or as an off-line tool, supporting separate estimation of the leakage components (sub-threshold, gate tunneling, reverse junction BTBT) including pattern dependency, stacking effects and loading effects. Results on single standard cells and multi-cell circuits exhibit a very good accuracy i.e. below 1% error with respect to Spice BSIM4. © 2011 IEEE
Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+)
No full textProcess variability are getting worse with the scaled technologies especially below 90 nm, therefore for the reliable fabrication outcome, the effect of both the local and global process variability should be taken into account. In this paper, verification, sizing and design centering/yield optimization for the robust second generation current controlled current conveyor (CCCII+) and CCCII+ based band pass filter for low power without degrading other performances values have been presented. Current conveyors (CC) based applications are getting significant attention in current analog ICs design due to their higher band-width, greater linearity, larger dynamic range, simpler circuitry, lower power consumption. Moreover CCCII has the advantage of electronic tunability at its intrinsic resistance terminal via a bias current. The net lists of CCCII+ and band pass filter circuits have been simulated in Eldo using the 65 nm CMOS mixed signal low-K TSMC process development kit (PDK) with 1.2 V, low-Vt devices with statistical models. All analysis, sizing and optimization have been performed using the WiCkeDTM tool at worst case operating conditions. Monte Carlo analysis has also been performed to verify the robustness of the circuit. © 2012 Elsevier Ltd. All rights reserved
Sizing and optimization of low power process variation aware standard cells
No full textThe yield of low voltage digital circuits based on standard cell design is found to be sensitive to local gate delay and power variations due to uncorrelated intra-die parameter fluctuations. Caused by random nature of doping positions they lead to more pronounced deviations for minimum transistor sizes. The basic idea of this work is to optimize the transistor level single standard cells by making the cells more resistant for process variations. © 2013 IEEE
Current controlled current conveyor (CCCII) and application using 65nm CMOS technology
No full textCurrent mode circuits like current conveyors are getting significant attention in current analog ICs design due to their higher band-width, greater linearity, larger dynamic range, simpler circuitry, lower power consumption and less chip area. The second generation current controlled conveyor (CCCII) has the advantage of electronic adjustability over the CCII i.e. in CCCII; adjustment of the X-terminal intrinsic resistance via a bias current is possible. The presented approach is based on the CMOS implementation of second generation positive (CCCII+), negative (CCCII-) and dual Output Current Controlled Conveyor (DOCCCII) and its application as Universal filter. All the circuits have been designed and simulated using 65nm CMOS technology model parameters on Cadence Virtuoso/Spectre using 1V supply voltage. Various simulations have been carried out to verify the linearity between output and input ports, range of operation frequency, etc. The outcomes show good agreement between expected and experimental results
Variability aware modeling of SEU induced failure probability of logic circuit paths in static conditions
No full textVoltage noise can lead to various errors such as dynamic and permanent, which are directly associated to circuit-level reliability issues. Variability in process parameters directly affects the probability of failures associated to voltage noise. Yet, the evaluation of the probability of failures by SPICE level Monte Carlo simulation is prohibitively time-consuming. This work proposes a technique to characterize the input noise and process variations in order to estimate failure probability in a logic circuit path composed of combinational cells and registers. The method allows to correctly estimate the order of magnitude of the probability of failures and to evidence the influence of process variations, while reaching >10(4) speedup versus SPICE
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