9 research outputs found
Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders
No full textIn this study, two asynchronous delay insensitive adder topologies in Null Convention Logic [1] style are adopted for bit-level pipelining: The reduced Null Convention Logic Adder [2] and a Null Convention Carry Save Adder. When pipelined at bit-level, early carry generation feature of both adders violate the requirements of delay insensitivity. To solve this problem, new topologies are proposed. Resultant adders maintain both reliable delay insensitive operation and speedup advantages of early carry generation, with O(log n) average completion time for n-bit addition and -as a result of bit-level pipelining- constant throughput against increased bit-length
Verification of delay insensitivity in bit-level pipelined dual-rail threshold logic adders
No full textA delay-insensitivity verification method is proposed for bit-level pipelined systolic dual-rail threshold logic adders, which achieve speed-up through early and input-incomplete carry output generation and which employ bit-wise completion at pipeline registers. The proposed method simplifies the verification task significantly, regardless of the operand length of the adder, such that analysis of three adjacent systoles for the eight possible early/late carry output generation scenarios is sufficient for detecting the input combinations which violate delay insensitivity. Using this method, structural modifications for re-establishing delay-insensitivity could be devised without sacrificing the speed-up advantages due to early carry generation. The method could also be applied to other pipelined data processing applications in dual-rail threshold logic
Verification of delay insensitivity in bit-level pipelined dual-rail threshold logic adders
No full textA delay-insensitivity verification method is proposed for bit-level pipelined systolic dual-rail threshold logic adders, which achieve speed-up through early and input-incomplete carry output generation and which employ bit-wise completion at pipeline registers. The proposed method simplifies the verification task significantly, regardless of the operand length of the adder, such that analysis of three adjacent systoles for the eight possible early/late carry output generation scenarios is sufficient for detecting the input combinations which violate delay insensitivity. Using this method, structural modifications for re-establishing delay-insensitivity could be devised without sacrificing the speed-up advantages due to early carry generation. The method could also be applied to other pipelined data processing applications in dual-rail threshold logic
Delay insensitivity verification of bit-level pipelined systolic arrays in dual-rail treshold logic
No full textSDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation
No full textA structural delay-insensitivity verification analysis method, SDIVA, is proposed for asynchronous systolic arrays in dual-rail threshold logic style. The SDIVA method employs symbolic delays for all output evaluation paths and works at the behavioral specification level. For bit-level pipelined systolic arrvys, which have data-dependent early output evaluation in one-dimension, SDIVA method reduces the verification analysis task to examination of three adjacent systoles so that by analyzing all possible early/late output evaluation scenarios on three systoles, the delay-insensitivity of a complete systolic array could be verified at once, regardless of the array dimensions. Delay-insensitivity violations are located and corrected at structural level, without diminishing the early output evaluation benefits. Since symbolic delays are used without imposing any timing assumptions on the environment; the SDIVA method is technology independent and robust against all physical and environmental variations
High data rate X-band transmitter for low Earth orbit satellites
No full textMain purpose of this study is to design a transmitter with data rates up to 100 Mbps, having QPSK/OQPSK modulation and 7 W (38.5 dBm) output power at 8.2 GHz. This output power satisfies the link budget for a low earth orbit (LEO) satellite at 700 km, utilizing required source-channel coding schemes in baseband for a BER performance of 10(-6). The modulation scheme of the transmitter can be selected as BPSK, QPSK or OQPSK. In addition to QPSK/OQPSK modulation scheme choice, the transmitter will have three different data rates, 50 Mbps and 100 Mbps which will be chosen according to the needs and facilities of the ground station. As error correction coding (ECC) scheme, a nested structure that is recommended by CCSDS is chosen which combines powerful parts of the subcodes. As the outer code, Reed Solomon with (255,223,33)(256) is used for error correction for burst errors due to multipath fading. As inner code, a convolutional code with rate (1/2) is utilized, which provides correction for random errors in the channel with a moderate bandwidth expansion. Between inner and outer codes, convolutional interleaver with depth 5 is used
High data rate X-band transmitter for low Earth orbit satellites
No full textMain purpose of this study is to design a transmitter with data rates up to 100 Mbps, having QPSK/OQPSK modulation and 7 W (38.5 dBm) output power at 8.2 GHz. This output power satisfies the link budget for a low earth orbit (LEO) satellite at 700 km, utilizing required source-channel coding schemes in baseband for a BER performance of 10(-6). The modulation scheme of the transmitter can be selected as BPSK, QPSK or OQPSK. In addition to QPSK/OQPSK modulation scheme choice, the transmitter will have three different data rates, 50 Mbps and 100 Mbps which will be chosen according to the needs and facilities of the ground station. As error correction coding (ECC) scheme, a nested structure that is recommended by CCSDS is chosen which combines powerful parts of the subcodes. As the outer code, Reed Solomon with (255,223,33)(256) is used for error correction for burst errors due to multipath fading. As inner code, a convolutional code with rate (1/2) is utilized, which provides correction for random errors in the channel with a moderate bandwidth expansion. Between inner and outer codes, convolutional interleaver with depth 5 is used
ÇOBAN: Design of Multi-Spectral Opto-Electronic Satellite Camera System
No full textCOBAN (an abbreviation for "multi-spectral camera" in Turkish) is a Multi-spectral Earth observing camera system developed for BiLSAT, a 129 kg micro-satellite, which was launched into a 686 km sun-synchronous orbit in 27 September 2003. COBAN is one of the two Turkish R&D payloads hosted by BiLSAT in addition to the two primary imager payloads (a 4 band multi-spectral 26 m Ground Sampling Distance (GSD) imager and a 12 m GSD panchromatic imager). The technical specification of COBAN can be summarized as follows: Number of spectral bands: 8. Ground Sampling Distance: 12 meter. Image size (in pixels): 640 x 480 (KODAK KAI-0311 CCD) Wavelengths of the bands: 375-425 nm, 410-490 nm, 460-540 nm, 510-590 nm, 560-640 nm, 610-690 nm, 660-740 nm, 850-1000 nm Aimed primarily as a tool for improving the capabilities for instrument design for space, COBAN successfully performed in space. However, the most important outcome has been the lessons learned from mistakes during design, manufacturing and testing, that will hopefully help us avoiding serious failures in future missions
